1. Technical Field
The present invention relates to semiconductor device fabrication, and more specifically, to implantation of gate regions in semiconductor device fabrication.
2. Related Art
A conventional semiconductor device fabrication process usually starts out with the formation of shallow trench device isolation (STI) followed by a gate dielectric formation on a semiconductor layer. Next, poly-silicon gate regions are formed on the gate dielectric layer. These poly-silicon gate regions are formed thick so that later source/drain and halo implantations cannot pass through them into the channel regions. The poly-silicon gate is doped by the same source/drain implants. The dose and the energy of the implants are optimized for the shallow source/drain diffusions and thus the doping concentration of the poly-silicon gate is not sufficient to reduce the poly-silicon depletion effect, and as a result, the effective electrical thickness of gate dielectric is significantly thicker than the physical gate dielectric thickness. Reducing the effective electrical thickness is one of the key factors to improve performance of poly-silicon gate field effect transistor (FET) device. Reducing the poly-silicon depletion thickness is essential to improve device performance. Therefore, it is highly beneficial to have a method to increase the concentration of doping of the poly-silicon without disturbing the optimized source/drain diffusion doping profile. One prior art method of optimizing both source/drain doping and poly-silicon gate doping is described by Dokumaci et al. in the U.S. patent application 2002/0197839A1. In this prior art, a spin-applied resist layer is formed on the entire structure and then etched back until the poly-silicon gate regions are exposed to the atmosphere. Next, gate regions implantation is performed to dope the gate regions. It is desirable that the spin-applied resist layer after being etched back is still thick enough to prevent the gate regions implantation from implanting regions of the semiconductor layer where source/drain regions will be later formed. However, the spin-applied resist layer, when formed, tends to be thicker where gate regions concentration is higher and tends to be thinner where gate regions concentration is lower. Therefore, after being etched back to expose the gate regions to the atmosphere, the spin-applied resist layer may be too thin where the pattern density of gate regions is lower to protect the semiconductor layer from the gate regions implantation.
As a result, there is a need for a structure (and method for forming the same), in which gate regions implantation essentially does not implant regions of the semiconductor layer where source/drain regions will be later formed.